The invention relates to a balanced enhancement/depletion mode buffer comparator circuit utilizing two pairs of close coupled gallium arsenide field effect transistors.
The article "A GaAs 4K Bit Static RAM with Normally-On and Off Combination Circuit", published in the IEEE Gallium Arsenide Integrated Circuit Symposuim, Technical Digest 1984, pp. 117-120, discloses a pass gated memory flip-flop shown in FIG. 1 wherein the data bus acts through the pass gates to cause the cross coupled enhancement mode FETs to switch states. The depletion mode FETs act only as constant current sources for the respective cross coupled E-Mode FETs.
Another circuit known from the prior art is shown in FIG. 2. In this circuit, additional E-Mode FETs are wired in parallel with the E-Mode FETs of FIG. 1. By pulsing the inputs of these E-Mode FETs independently, the pulsed FETs can be made to overdrive their respective outputs to ground, forcing the flip-flop to assume a new state.
The aforementioned RAM cell shown in FIG. 1 requires the data bus to overdrive its output to produce a new state for the flip-flop. The D-Mode FETs are always "on" providing a bias for the cross coupled E-Mode FETs one of which is always "on" to overdrive the bias current to achieve a low voltage output. Thus power is not used efficiently.
The aforementioned flip-flop shown in FIG. 2 utilizes a wired OR FET to overdrive the output to cause a state change, thus buffering the inputs. However the FET bias current must still be overdriven to achieve a logic low output voltage with the same power dissipation as the aforementioned RAM cell. This situation is aggravated by the higher bias currents of wired OR FETs. This circuit requires six active devices, two more than the RAM cell.